The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 05, 2013

Filed:

May. 26, 2011
Applicants:

Chih Ching Lin, Taoyuan, TW;

Yi Nan Chen, Taipei, TW;

Hsien Wen Liu, Luzhu Township, TW;

Inventors:

Chih Ching Lin, Taoyuan, TW;

Yi Nan Chen, Taipei, TW;

Hsien Wen Liu, Luzhu Township, TW;

Assignee:

Nanya Technology Corporation, Kueishan, Tao-Yuan Hsien,, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of via formation in a semiconductor device includes the following steps of providing a photoresist with a photoresist pattern defining an opening of a via, wherein the photoresist comprising a thermally cross-linking material is disposed on a structure layer; dry-etching the structure layer to a first depth through the opening; baking the thermally cross-linking material to reduce the opening; and dry-etching the structure layer to a second depth through the reduced opening, wherein the second depth is greater than the first depth.


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Lin, Chih. (2013). Method for via formation in a semiconductor device (U.S. Patent No. 8389402). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8389402

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