The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2013

Filed:

Jul. 02, 2008
Applicants:

Rong N. Chang, Pleasantville, NY (US);

Klaus Sonnenleiter, Franklin Lakes, NJ (US);

Chunqiang Tang, Ossining, NY (US);

Sunjit Tara, Budd Lake, NJ (US);

Chun Zhang, Ossining, NY (US);

Inventors:

Rong N. Chang, Pleasantville, NY (US);

Klaus Sonnenleiter, Franklin Lakes, NJ (US);

Chunqiang Tang, Ossining, NY (US);

Sunjit Tara, Budd Lake, NJ (US);

Chun Zhang, Ossining, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
Abstract

Throughput of a high-volume throughput-centric computer system is controlled by dynamically adjusting a concurrency level of a plurality of events being processed in a computer system to meet a predetermined target for utilization of one or more resources of a computer system. The predetermined target is less than 100% utilization of said one or more resources. The adjusted concurrency level is validated using one or more queuing models to check that said predetermined target is being met. Parameters are configured for adjusting the concurrency level. The parameters are configured so that said one or more resources are shared with one or more external programs. A statistical algorithm is established that minimizes total number of samples collected. The samples may be used to measure performance used to further dynamically adjust the concurrency level. A dynamic thread sleeping method is designed to handle systems that need only a very small number of threads to saturate bottleneck resources and hence are sensitive to concurrency level changes.


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