The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 26, 2013
Filed:
Aug. 10, 2010
Christopher H. Kingsley, Longmont, CO (US);
George L. Mchugh, Berthoud, CO (US);
Christopher H. Kingsley, Longmont, CO (US);
George L. McHugh, Berthoud, CO (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
In one embodiment, a method for parallel routing of a circuit design is provided. Placement of a netlist of the circuit design is determined for a target device. A plurality of regions of the target device is defined. Each region of the plurality of regions is assigned to a respective set of processors, each set including at least one processor. Global routing of nets of the netlist on the target device is performed. The global routing of each net restricts the net to one or more possible routes through a corresponding subset of the plurality of regions. Local routing of the netlist is concurrently performed within the plurality of regions using the respective sets of processors. Within each region, the local routing of the netlist is performed exclusively by the respective set of one or more processors.