The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 26, 2013
Filed:
Mar. 16, 2010
Uwe Dannowski, Moritzburg, DE;
Stephan Diestelhorst, Dresden, DE;
Sebastian Biemueller, Dresden, DE;
Uwe Dannowski, Moritzburg, DE;
Stephan Diestelhorst, Dresden, DE;
Sebastian Biemueller, Dresden, DE;
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A processing system has one or more processors that implement a plurality of virtual machines that are managed by a hypervisor. Each virtual machine provides a secure and isolated hardware-emulation environment for execution of one or more corresponding guest operating systems (OSs). Each guest OS, as well as the hypervisor itself, has an associated address space, identified with a corresponding 'WorldID.' Further, each virtual machine and the hypervisor can manage multiple lower-level address spaces, identified with a corresponding 'address space identifier' or “ASID”. The address translation logic of the processing system translates the WorldID and ASID of the current address space context of the processing system to corresponding WorldID and ASID search keys, which have fewer bits than the original identifiers and thus require less complex translation lookaside buffer (TLB) hit logic. The resulting WorldID and ASID search keys are used to perform one or more TLB lookups to obtain address mapping information related to the particular address space represented by the WorldID/ASID combination.