Multi-port, gigabit serdes transceiver capable of automatic fail switchover

Abstract

A multi-port Serdes transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any of the parallel ports to another parallel port or to a serial port, or both. Furthermore, the transceiver can connect any of the serial ports to another serial port or to a parallel port. The transceiver further includes a switch, a logic core, and a bus. The switch is selectively coupled to at least a first port and a second port. The switch activates the first port and deactivates the second port based on satisfaction of a condition associated with the first port. The logic core operates the serial and parallel ports, and the bus connects the ports. The bus can be described as a 'ring' structure (or donut 'structure') around the logic core, and is configured between the logic core and the ports. The ring structure provides efficient communication between the logic core and the ports.