The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 26, 2013
Filed:
Sep. 13, 2010
William Hall Coley, Cary, NC (US);
Charles Edward Hawkes, Cary, NC (US);
William Hall Coley, Cary, NC (US);
Charles Edward Hawkes, Cary, NC (US);
Linear Technology Corporation, Milpitas, CA (US);
Abstract
Novel system and methodology are provided for controlling a DC/DC forward converter having a transformer with primary and secondary windings, a reset switch, and a first switch coupled to the primary winding of the transformer. The control system involves a PWM control circuit responsive to an output signal of the converter for producing a PWM signal to control switching of the reset switch, and the first switch. A period of the PWM signal includes an on-time interval for enabling transfer of power via the transformer when the first switch is on, and a reset time interval for enabling reset of the transformer when the reset switch is on. A maximum value of the on-time interval is pre-set to provide sufficient time for the reset. The reset switch is turned off when the PWM signal goes from a first level to a second level. A first delay period is set between time when the reset switch turns off and time when the first switch turns on. A first delay control circuit is provided for reducing the first delay time when the on-time interval approaches the maximum value. Further, the converter may include a second switch coupled to the secondary winding of the transformer. A second delay period shorter than the first delay period may be set between time when the reset switch turns off and time when the second switch turns on. A second delay control circuit may be provided for reducing the second delay period when the on-time interval approaches the maximum value.