The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2013

Filed:

Sep. 13, 2011
Applicants:

Kevin Parker, Nepean, CA;

Malcolm Stevens, North Gower, CA;

Stephane Dallaire, Gatineau, CA;

Shawn Scouten, Kanata, CA;

Jeff P. Kirsten, Folsom, CA (US);

Inventors:

Kevin Parker, Nepean, CA;

Malcolm Stevens, North Gower, CA;

Stephane Dallaire, Gatineau, CA;

Shawn Scouten, Kanata, CA;

Jeff P. Kirsten, Folsom, CA (US);

Assignee:

Cortina Systems, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A phase difference between a reference clock signal and a feedback signal is digitally detected. A resultant phase detection signal is digitally filtered, and a PLL (Phase Locked Loop) output signal is synthesized in a fractional synthesizer under control of the digitally filtered phase detection signal. A feedback path, which could include an integer divider and/or a fractional N divider, provides the feedback signal based on the PLL output signal. The combination of a wide bandwidth fractional synthesizer and a low bandwidth digital PLL provides for a low bandwidth jitter filtering function with a wide bandwidth PLL to suppress VCO (Voltage Controlled Oscillator) noise and crosstalk.


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