The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 26, 2013

Filed:

Mar. 04, 2010
Applicants:

Scott R. Summerfelt, Garland, TX (US);

Ted S. Moise, Dallas, TX (US);

Gul B. Basim, Mountain View, CA (US);

Inventors:

Scott R. Summerfelt, Garland, TX (US);

Ted S. Moise, Dallas, TX (US);

Gul B. Basim, Mountain View, CA (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit that includes a logic region, a buffer region, and a ferroelectric capacitor region that contains ferroelectric capacitors. The integrated circuit also includes a hydrogen diffusion barrier film that overlies ferroelectric capacitors and also overlies a buffer region located between a ferroelectric capacitor region and a logic region. However, the hydrogen diffusion barrier film is removed from a portion of the logic region. Moreover, a method for forming a hydrogen barrier layer that overlies ferroelectric capacitors and a buffer region but is removed from a portion of the logic region.


Find Patent Forward Citations

Summerfelt, Scott. (2013). Passivation of integrated circuits containing ferroelectric capacitors and hydrogen barriers (U.S. Patent No. 8384190). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8384190

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…