Defect prevention on sram cells that incorporate selective epitaxial regions

Abstract

An SRAM device and method of forming MOS transistors of the device having reduced defects associated with selective epitaxial growth in moat tip regions is discussed. The SRAM device comprises a core region and a logic region, logic transistors within the logic region of the SRAM, and selective epitaxial regions grown on both source and drain regions; and memory cell transistors within the core region of the SRAM, and having the selective epitaxial regions grown on only one of the source and drain regions. One method of forming the MOS transistors of the SRAM cell comprises forming a gate structure over a first conductivity type substrate to define a channel therein, masking one of the source and drain regions in the core region, forming a recess in the substrate of the unmasked side of the channel, epitaxially growing SiGe in the recess, removing the mask, and forming the source and drain extension regions in source/drain regions.