The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 26, 2013
Filed:
Aug. 27, 2010
Yong-duck Son, Yongin, KR;
Ki-yong Lee, Yongin, KR;
Joon-hoo Choi, Yongin, KR;
Min-jae Jeong, Yongin, KR;
Seung-kyu Park, Yongin, KR;
Kil-won Lee, Yongin, KR;
Jae-wan Jung, Yongin, KR;
Dong-hyun Lee, Yongin, KR;
Byung-soo SO, Yongin, KR;
Hyun-woo Koo, Yongin, KR;
Ivan Maidanchuk, Yongin, KR;
Jong-won Hong, Yongin, KR;
Heung-yeol NA, Yongin, KR;
Seok-rak Chang, Yongin, KR;
Yong-Duck Son, Yongin, KR;
Ki-Yong Lee, Yongin, KR;
Joon-Hoo Choi, Yongin, KR;
Min-Jae Jeong, Yongin, KR;
Seung-Kyu Park, Yongin, KR;
Kil-Won Lee, Yongin, KR;
Jae-Wan Jung, Yongin, KR;
Dong-Hyun Lee, Yongin, KR;
Byung-Soo So, Yongin, KR;
Hyun-Woo Koo, Yongin, KR;
Ivan Maidanchuk, Yongin, KR;
Jong-Won Hong, Yongin, KR;
Heung-Yeol Na, Yongin, KR;
Seok-Rak Chang, Yongin, KR;
Samsung Display Co., Ltd., Yongin, Gyeonggi-Do, KR;
Abstract
A thin film transistor includes a substrate, a buffer layer on the substrate, a semiconductor layer including source/drain regions and a channel region on the buffer layer, a gate insulating layer corresponding to the channel region, a gate electrode corresponding to the channel region, and source/drain electrodes electrically connected to the semiconductor layer. A polysilicon layer of the channel region may include only a low angle grain boundary, and a high angle grain boundary may be disposed in a region of the semiconductor layer that is apart from the channel region.