The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 19, 2013
Filed:
Mar. 03, 2010
Frederick C. Jen, Santa Clara, CA (US);
LI Qiu, Santa Clara, CA (US);
Hsiu C. MA, Santa Clara, CA (US);
Calvin V. Ho, Santa Clara, CA (US);
Xiang M. Song, Santa Clara, CA (US);
Hsiaohui Wu, Santa Clara, CA (US);
Thomas E. Little, Santa Clara, CA (US);
Frederick C. Jen, Santa Clara, CA (US);
Li Qiu, Santa Clara, CA (US);
Hsiu C. Ma, Santa Clara, CA (US);
Calvin V. Ho, Santa Clara, CA (US);
Xiang M. Song, Santa Clara, CA (US);
Hsiaohui Wu, Santa Clara, CA (US);
Thomas E. Little, Santa Clara, CA (US);
QUALCOMM Incorporated, San Diego, CA (US);
Abstract
A system and method to select a gate to be modified as a test isolation gate is disclosed. In a particular embodiment, a method includes, after a layout phase of generating a design of a circuit, receiving timing information related to the design of the circuit. The method also includes selectively identifying at least one gate of a combinational logic portion of the design of the circuit to be modified to respond to a test enable signal, the at least one gate identified at least partially based on the timing information. The method also includes modifying the at least one gate. The at least one modified gate is fixed at a constant level during a test mode and is dynamically changeable during a functional mode of operation of the circuit.