The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2013

Filed:

Jul. 29, 2010
Applicants:

Yong Ju Kim, Icheon-si, KR;

Dae Han Kwon, Icheon-si, KR;

Won Joo Yun, Icheon-si, KR;

Hae Rang Choi, Icheon-si, KR;

Jae Min Jang, Icheon-si, KR;

Inventors:

Yong Ju Kim, Icheon-si, KR;

Dae Han Kwon, Icheon-si, KR;

Won Joo Yun, Icheon-si, KR;

Hae Rang Choi, Icheon-si, KR;

Jae Min Jang, Icheon-si, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A clock signal duty correction circuit includes: a first transition timing control unit configured to generate a first control signal for controlling a rising timing of a duty correction clock signal by using a clock signal; a second transition timing control unit configured to generate a second control signal for varying a falling timing of the duty correction clock signal by using the clock signal according to a code signal; and a differential buffer unit configured to generate the duty correction clock signal, whose rising time or falling time is adjusted, in response to the first control signal and the second control signal.


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