The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 19, 2013

Filed:

Jul. 18, 2008
Applicants:

Paul Ronald Stribley, Devon, GB;

Mark Parsons, Devon, GB;

Graham Chapman, Devon, GB;

Inventors:

Paul Ronald Stribley, Devon, GB;

Mark Parsons, Devon, GB;

Graham Chapman, Devon, GB;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/92 (2006.01);
U.S. Cl.
CPC ...
Abstract

A device comprises a substrate (); a first MiM capacitor () disposed over the substrate; and a second MiM capacitor () disposed over the first MiM capacitor. The first MiM capacitor and the second MiM capacitor are electrically connected in parallel. The two MiM capacitors are vertically stacked one above the other. Each MiM capacitor comprises an interconnection layer (') of the CMOS process as one plate and a thinner conductive layer (′) as the second plate, with an insulating layer (′) disposed therebetween. This allows each MiM capacitor to be formed between two CMOS process interconnection layers. The second plate of the second MiM capacitor is substantially co-extensive with the second plate of the first MiM capacitor, and is disposed substantially directly over the second plate of the first MiM capacitor. The same mask may be used to pattern the second plate of the second MiM capacitor and the second plate of the first MiM capacitor. This minimizes the number of masks required, and so minimizes the mask investment cost.


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