The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 19, 2013
Filed:
Jun. 30, 2011
Gayle W. Miller, Colorado Springs, CO (US);
Volker Dudek, Brackenheim, DE;
Michael Graf, Leutenbach, DE;
Gayle W. Miller, Colorado Springs, CO (US);
Volker Dudek, Brackenheim, DE;
Michael Graf, Leutenbach, DE;
Atmel Corporation, San Jose, CA (US);
Abstract
By aligning the primary flat of a wafer with a () plane rather than a () plane, devices can be formed with primary currents flowing along the () plane. In this case, the device will intersect the () plane at approximately 54.7 degrees. This intersect angle significantly reduces stress propagation/relief along the () direction and consequently reduces defects as well as leakage and parasitic currents. The leakage current reduction is a direct consequence of the change in the dislocation length required to short the source-drain junction. By using this technique the leakage current is reduced by up to two orders of magnitude for an N-channel CMOS device.