The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 19, 2013
Filed:
Aug. 17, 2010
Weize Xiong, Plano, TX (US);
Greg Charles Baldwin, Plano, TX (US);
Weize Xiong, Plano, TX (US);
Greg Charles Baldwin, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
Various embodiments provide methods for fabricating dual supply voltage CMOS devices with a desired I/O transistor threshold voltage. The dual supply voltage CMOS devices can be fabricated in a semiconductor substrate that includes isolated regions for a logic NMOS transistor, a logic PMOS transistor, an I/O NMOS transistor, and an I/O PMOS transistor. Specifically, the fabrication can first set and/or adjust the threshold voltage (V) of each of the I/O NMOS transistor and the I/O PMOS transistor to a desired level. Logic NMOS and logic PMOS transistors can then be formed with I/O NMOS and I/O PMOS transistors masked without affecting the set/adjusted Vof the I/O transistors.