The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 19, 2013
Filed:
Jul. 26, 2011
Stephen Daley Arthur, Glenville, NY (US);
Kevin Matocha, Starkville, MS (US);
Peter Sandvik, Niskayuna, NY (US);
Zachary Stum, Niskayuna, NY (US);
Peter Losee, Rensselaer, NY (US);
James Mcmahon, Clifton Park, NY (US);
Stephen Daley Arthur, Glenville, NY (US);
Kevin Matocha, Starkville, MS (US);
Peter Sandvik, Niskayuna, NY (US);
Zachary Stum, Niskayuna, NY (US);
Peter Losee, Rensselaer, NY (US);
James McMahon, Clifton Park, NY (US);
General Electric Company, Niskayuna, NY (US);
Abstract
In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well () (P type) and two parallel sources () (N type) formed within the well. A plurality of source rungs () (doped N) connect sources () at multiple locations. Regions between two rungs () comprise a body () (P type). These features are formed on an N-type epitaxial layer (), which is formed on an N-type substrate (). A contact () extends across and contacts a plurality of source rungs () and bodies (). Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.