The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2013

Filed:

Apr. 16, 2010
Applicants:

Eddie K. Chan, Austin, TX (US);

Michael J. Lee, Austin, TX (US);

Ricardo H. Nigaglioni, Austin, TX (US);

Bao G. Truong, Austin, TX (US);

Inventors:

Eddie K. Chan, Austin, TX (US);

Michael J. Lee, Austin, TX (US);

Ricardo H. Nigaglioni, Austin, TX (US);

Bao G. Truong, Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G11C 11/00 (2006.01); G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A mechanism is provided for enabling a proper write through during a write-through operation. Responsive to determining the memory access as a write-through operation, first circuitry determines whether a data input signal is in a first state or a second state. Responsive to the data input signal being in the second state, the first circuitry outputs a global write line signal in the first state. Responsive to the global write line signal being in the first state, second circuitry outputs a column select signal in the second state. Responsive to the column select signal being in the second state, third circuitry keeps a downstream read path of the cache access memory at the first state such that data output by the cache memory array is in the first state.


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