The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 12, 2013
Filed:
Feb. 12, 2010
Christopher William Laycock, Sheffield, GB;
Antony John Harris, Hope Valley, GB;
Bruce James Mathewson, Papworth Everard, GB;
Andrew Christopher Rose, Cambridge, GB;
Richard Roy Grisenthwaite, Guilden Morden, GB;
Christopher William Laycock, Sheffield, GB;
Antony John Harris, Hope Valley, GB;
Bruce James Mathewson, Papworth Everard, GB;
Andrew Christopher Rose, Cambridge, GB;
Richard Roy Grisenthwaite, Guilden Morden, GB;
ARM Limited, Cambridge, GB;
Abstract
A data processing apparatus for forming a portion of a coherent cache system comprises at least one master device for performing data processing operations, and a cache coupled to the at least one master device and arranged to store data values for access by that at least one master device when performing the data processing operations. Cache coherency circuitry is responsive to a coherency request from another portion of the coherent cache system to cause a coherency action to be taken in respect of at least one data value stored in the cache. Responsive to an indication that the coherency action has resulted in invalidation of that at least one data value in the cache, refetch control circuitry is used to initiate a refetch of that at least one data value into the cache. Such a mechanism causes the refetch of data into the cache to be triggered by the coherency action performed in response to a coherency request from another portion of the coherent cache system, rather than relying on any actions taken by the at least one master device, thereby providing a very flexible and efficient mechanism for reducing cache latency in a coherent cache system.