The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 12, 2013
Filed:
Jun. 17, 2009
Hae Rang Choi, Gyeonggi-do, KR;
Yong Ju Kim, Gyeonggi-do, KR;
Sung Woo Han, Gyeonggi-do, KR;
Hee Woong Song, Gyeonggi-do, KR;
Ic Su OH, Gyeonggi-do, KR;
Hyung Soo Kim, Gyeonggi-do, KR;
Tae Jin Hwang, Gyeonggi-do, KR;
Ji Wang Lee, Gyeonggi-do, KR;
Jae Min Jang, Gyeonggi-do, KR;
Chang Kun Park, Gyeonggi-do, KR;
Hae Rang Choi, Gyeonggi-do, KR;
Yong Ju Kim, Gyeonggi-do, KR;
Sung Woo Han, Gyeonggi-do, KR;
Hee Woong Song, Gyeonggi-do, KR;
Ic Su Oh, Gyeonggi-do, KR;
Hyung Soo Kim, Gyeonggi-do, KR;
Tae Jin Hwang, Gyeonggi-do, KR;
Ji Wang Lee, Gyeonggi-do, KR;
Jae Min Jang, Gyeonggi-do, KR;
Chang Kun Park, Gyeonggi-do, KR;
Hynix Semiconductor Inc., Gyeonggi-do, KR;
Abstract
The domain crossing circuit of a semiconductor memory apparatus for improving a timing margin includes a sampler that provides a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and an edge information signal that defines an output timing of the sampling internal signal and an output stage that allows the sampling internal signal to be synchronized with the clock in response to the edge information signal to be output as a final output signal.