The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2013

Filed:

Sep. 20, 2011
Applicants:

John A. Milinichik, Allentown, PA (US);

Peter J. Nicholas, Philadelphia, PA (US);

Carol A. Huber, Macungie, PA (US);

Antonio M. Marques, Newark, NJ (US);

Daniel J. Delpero, Allentown, PA (US);

Inventors:

John A. Milinichik, Allentown, PA (US);

Peter J. Nicholas, Philadelphia, PA (US);

Carol A. Huber, Macungie, PA (US);

Antonio M. Marques, Newark, NJ (US);

Daniel J. Delpero, Allentown, PA (US);

Assignee:

LSI Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H03K 19/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Described embodiments provide for a semiconductor device comprising a core and one or more input/output (I/O) buffers surrounding the core. The I/O buffers are adapted to transfer signals associated with core circuitry of the core. The I/O buffers comprise I/O cells having a first orientation and I/O cells having a second orientation. Each I/O cell has a corresponding translator having low voltage transistors in a corresponding footprint. The low voltage transistors in the first orientation I/O cells have the first orientation, and the low voltage transistors in the second orientation I/O cells have the first orientation. The footprints of the first orientation I/O cells and the second orientation I/O cells are compatible with one another.


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