The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8373274 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 12, 2013

Filed:

Feb. 15, 2008
Applicants:

Hisaya Sakai, Kawasaki, JP;

Noriyoshi Shimizu, Kawasaki, JP;

Inventors:

Hisaya Sakai, Kawasaki, JP;

Noriyoshi Shimizu, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
Abstract

A micronized wiring structure is obtained by optimizing film forming modes of barrier metal films as being adapted respectively to a via-hole and a wiring groove, wherein sputtering processes are adopted herein, which are specifically the multi-step sputtering process for formation of the barrier metal film over the via-hole, and the one-step, low-power sputtering process for formation of the barrier metal film over the wiring groove, to thereby realize improved electric characteristics such as via-hole resistance and wiring resistance, and improved wiring reliabilities such as Cu filling property and electro-migration resistance.


Find Patent Forward Citations

Sakai, Hisaya. (2013). Method of forming wiring structure and semiconductor device comprising underlying refractory metal layers (U.S. Patent No. 8373274). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8373274

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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