The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 12, 2013

Filed:

Sep. 28, 2009
Applicants:

Kiyoaki Kudo, Moriguchi, JP;

Takashi Shibasaki, Moriguchi, JP;

Tetsuya Yamamoto, Hashima, JP;

Inventors:

Kiyoaki Kudo, Moriguchi, JP;

Takashi Shibasaki, Moriguchi, JP;

Tetsuya Yamamoto, Hashima, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/74 (2006.01); H01L 23/495 (2006.01); H01L 23/10 (2006.01); H01L 23/34 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided is a circuit device having a configuration in which thermal interference between built-in elements is suppressed and being miniaturized in total size. A hybrid integrated circuit device of the present invention includes: a circuit substrate, a sealing resin and leads. The circuit substrate in its upper surface is incorporated with a hybrid integrated circuit formed of semiconductor elements and the like respectively fixed to heat spreaders. The sealing resin coats the circuit substrate and thus seals the hybrid integrated circuit. The leads each extend to the outside while being fixed to a pad formed of a conductive pattern. In this hybrid integrated circuit device, the semiconductor elements are mounted on the respective heat spreaders at positions offset from each other, and thereby are arranged to be spaced away from each other.


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