Pipelined adc having error correction

Abstract

A pipeline stage of a pipelined analog-to-digital converter (ADC) circuit can include an ADC to convert an analog input to a digital output, a first plurality of digital-to-analog converters (DACs) sufficient in number to produce an analog output corresponding to the digital output, and a second plurality of DACs configured to have their output added into the analog output, where a succeeding pipeline portion can convert the amplified analog residue to at least one second digital output and a digitized residue. A mapping circuit can selectively exchange inputs between a selected one of the first plurality of DACs and one of the second plurality of DACs, and a calibration signal circuit can provide first and second calibration signals to inputs of the selected one of the first plurality of DACs and another of the second plurality of DACs. The calibration signals can be correlated to each other, but uncorrelated to the analog input and digital output of the first pipeline stage, and have unequal effects on the amplified analog residue or the digitized residue. A correction circuit can correct the digital output of the pipeline stage for circuit path errors in circuit paths including the first plurality and second plurality of DACs based on the results of a correlation between the calibration signals and the second digital output or digitized residue. The effects, on the amplified analog residue or the digitized residue, of the first and second calibration signals, upon travelling through the selected one of the first plurality of DACs and the other of the second plurality of DACs, can at least partially offset each other.