The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2013

Filed:

Jan. 05, 2010
Applicants:

Hisashi Tanie, Mito, JP;

Takeyuki Itabashi, Hitachi, JP;

Nobuhiko Chiwata, Matsue, JP;

Motoki Wakano, Yasugi, JP;

Inventors:

Hisashi Tanie, Mito, JP;

Takeyuki Itabashi, Hitachi, JP;

Nobuhiko Chiwata, Matsue, JP;

Motoki Wakano, Yasugi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device having stacked semiconductor chips is provided wherein alignment of even thin semiconductor chips of a large warpage is easy and thus high assembling accuracy and high reliability are ensured. Semiconductor chips having hollow through-silicon via electrodes each formed with a tapered portion are melt-joined using solder balls each having a core of a material higher in melting point than solder. When melt-joining the semiconductor chips, the temperature is raised while imparting an urging load to stacked semiconductor chips, thereby correcting warpage of the semiconductor chips. In each chip-to-chip connection thus formed, if the connection is to prevent the occurrence of stress around the electrode due to the urging load, a solder ball having a core of a smaller diameter than in the other connections is used in the connection.


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