The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8367559 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 05, 2013

Filed:

Jan. 25, 2011
Applicants:

Hironori Yamamoto, Kanagawa, JP;

Yoshihiro Hayashi, Kanagawa, JP;

Inventors:

Hironori Yamamoto, Kanagawa, JP;

Yoshihiro Hayashi, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/31 (2006.01);
U.S. Cl.
CPC ...
Abstract

Characteristics of a low-k insulating film grown on a substrate is modulated in the thickness-wise direction, by varying the ratio of high-frequency input and low-frequency input used for inducing plasma in the course of forming the film, to thereby improve the adhesion strength while keeping the dielectric constant at a low level, wherein the high-frequency input and the low-frequency input for inducing plasma are applied from a single electrode, while elevating the level of low-frequency input at least either at the start of formation or at the end of formation of the insulating film, as compared with the input level in residual time zone.


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Yamamoto, Hironori. (2013). Method of manufacturing a semiconductor device (U.S. Patent No. 8367559). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8367559

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