Supporting method, design supporting device, computer product, and semiconductor integrated circuit

Abstract

A method executed by a computer and for designing a semiconductor integrated circuit, includes detecting, from layout data of a semiconductor integrated circuit, a clock path that propagates the clock signal and of which clock buffers are single-gate inverting clock buffers; selecting sequentially data holding elements connected to the detected clock path; identifying an input clock buffer of each selected data holding element; determining whether the identified clock buffer outputs the clock signal according to non-inverting logic or inverting logic, based on the number of gates from the clock source to the clock buffer; replacing, based on a determination result, the data holding element with a first data holding element that takes in data in synchronization with a rising edge of the clock signal or with a second data holding element that takes in data in synchronization with a falling edge of the clock signal; and outputting a replacement result.