The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2013

Filed:

Apr. 23, 2007
Applicants:

Dennis E. Dudeck, Hazleton, PA (US);

Donald Albert Evans, Lancaster, OH (US);

Hai Quang Pham, Hatfield, PA (US);

Wayne E. Werner, Coopersburg, PA (US);

Ronald James Wozniak, Allentown, PA (US);

Inventors:

Dennis E. Dudeck, Hazleton, PA (US);

Donald Albert Evans, Lancaster, OH (US);

Hai Quang Pham, Hatfield, PA (US);

Wayne E. Werner, Coopersburg, PA (US);

Ronald James Wozniak, Allentown, PA (US);

Assignee:

Agere Systems Inc., Allentown, PA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory device comprises a memory array and error correction circuitry coupled to the memory array. The error correction circuitry is configured to identify, in a data word retrieved from the memory array, at least one bit position corresponding to a predetermined defect location in the memory array, and to generate a corrected data word by automatically inverting a logic value at the identified bit position. This automatic logic inversion approach is particularly well suited for use in correcting output data errors associated with via defects and weak bit defects in high-density ROM devices.


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