The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 29, 2013
Filed:
Apr. 12, 2010
William J. Armstrong, Rochester, MN (US);
Scott N. Dunham, Raleigh, NC (US);
David R. Engebretsen, Cannon Falls, MN (US);
Gregory M. Nordstrom, Pine Island, MN (US);
Steven M. Thurber, Austin, TX (US);
Curtis C. Wollbrink, Rochester, MN (US);
Adalberto G. Yanes, Rochester, MN (US);
William J. Armstrong, Rochester, MN (US);
Scott N. Dunham, Raleigh, NC (US);
David R. Engebretsen, Cannon Falls, MN (US);
Gregory M. Nordstrom, Pine Island, MN (US);
Steven M. Thurber, Austin, TX (US);
Curtis C. Wollbrink, Rochester, MN (US);
Adalberto G. Yanes, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
In an embodiment, a translation of a hierarchical MMIO address range to a physical MMIO address range and an identifier of a bridge in a south chip are written to a north chip. A transaction is received that comprises a hierarchical MMIO address. The hierarchical MMIO address that is within the hierarchical MMIO address range is replaced in the transaction with the identifier of the bridge and with a physical MMIO address that is within the physical MMIO address range in the south chip. The transaction is sent to the device that is connected to the bridge in the south chip. The physical MMIO address range specifies a range of physical MMIO addresses in memory in the device.