The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8362624 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 29, 2013

Filed:

Sep. 12, 2011
Applicants:

Tae-ho Kang, Seoul, KR;

Jin-ho Kim, Cheonan-si, KR;

Bo-seong Kim, Seoul, KR;

Inventors:

Tae-Ho Kang, Seoul, KR;

Jin-Ho Kim, Cheonan-si, KR;

Bo-Seong Kim, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/02 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided are a multi-chip package and a method of manufacturing the same, which can facilitate wire bonding even when an upper chip is larger than a lower chip or overhangs a lower chip. A multi-chip package includes a substrate having first and second bonding pads on a top surface thereof, a first chip connected to the first bonding pads on the substrate, an insulating layer formed on the substrate so as to surround lateral surfaces of the first chip, a set of openings formed in the insulating layer so as to expose the second bonding pads, and a second chip formed on the insulating layer and the first chip, the second chip having a larger area than the first chip and connected to the second bonding pads using wires that pass through the second openings.


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