The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 29, 2013

Filed:

Dec. 29, 2010
Applicant:

Yong-kuk Jeong, Suwon-si, KR;

Inventor:

Yong-Kuk Jeong, Suwon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
Abstract

A transistor includes a silicon germanium channel layer formed on a portion of a single crystalline silicon substrate. The silicon germanium channel layer includes a Si—H bond and/or a Ge—H bond at an inner portion or an upper surface portion thereof. A PMOS transistor is provided on the silicon germanium channel layer. A silicon nitride layer is provided on surface portions of the single crystalline silicon substrate, the silicon germanium channel layer and the PMOS transistor for applying a tensile stress. The MOS transistor shows good operating characteristics.


Find Patent Forward Citations

Jeong, Yong-Kuk. (2013). Methods of manufacturing cmos transistors (U.S. Patent No. 8361852). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8361852

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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