The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 22, 2013
Filed:
Jul. 27, 2012
Masuyuki Ohta, Mobara, JP;
Kazuhiro Ogawa, Mobara, JP;
Keiichiro Ashizawa, Mobara, JP;
Kazuhiko Yanagawa, Mobara, JP;
Masahiro Yanai, Mobara, JP;
Nobutake Konishi, Mobara, JP;
Nobuyuki Suzuki, Mobara, JP;
Masahiro Ishii, Mobara, JP;
Makoto Yoneya, Hitachinaka, JP;
Sukekazu Aratani, Hitachiohta, JP;
Masuyuki Ohta, Mobara, JP;
Kazuhiro Ogawa, Mobara, JP;
Keiichiro Ashizawa, Mobara, JP;
Kazuhiko Yanagawa, Mobara, JP;
Masahiro Yanai, Mobara, JP;
Nobutake Konishi, Mobara, JP;
Nobuyuki Suzuki, Mobara, JP;
Masahiro Ishii, Mobara, JP;
Makoto Yoneya, Hitachinaka, JP;
Sukekazu Aratani, Hitachiohta, JP;
Hitachi Displays, Ltd., Chiba, JP;
Panasonic Liquid Crystal Display Co., Ltd., Hyogo-ken, JP;
Abstract
A liquid crystal display device includes first and second substrates, a liquid crystal layer disposed therebetween, pixel regions formed by gate signal lines and image signal lines formed over the first substrate, a first insulating layer formed over the gate signal lines, thin film transistors connected to the gate signal lines with in a second insulating layer formed thereover, pixel electrodes connected to the thin film transistors, a counter electrode formed of a first transparent conductive layer over the second insulating layer, and a second transparent conductive layer and an external connection terminal disposed outside of the pixel regions. The second transparent conductive layer is formed over the second insulating layer and is electrically connected to the counter electrode and the external connection terminal, and a part of each of the gate signal lines is disposed outside of the pixel regions and is covered by the second transparent conductive layer.