The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 22, 2013

Filed:

May. 15, 2009
Applicants:

Hao Wang, Shanghai, CN;

Wai Tung NG, Thornhill, CA;

Huaping Xu, North York, CA;

Inventors:

Hao Wang, Shanghai, CN;

Wai Tung Ng, Thornhill, CA;

Huaping Xu, North York, CA;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/732 (2006.01);
U.S. Cl.
CPC ...
Abstract

An orthogonal gate extended drain MOSFET (EDMOS) structure provides a low gate-to-drain capacitance (C) and exhibits increased reliability. It has a gate electrode that is folded into the shallow trench isolation (STI) oxide region. Horizontal and vertical gate electrode segments provide gate control. It accommodates both high voltage devices and standard CMOS components on the same substrate. Reduced surface field (RESURF) technology is employed to optimize tradeoffs between high breakdown voltage and specific on-resistance. Device fabrication steps are compatible with standard CMOS flow and process modules can be added or removed from baseline CMOS technology.


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