The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 22, 2013
Filed:
Aug. 10, 2006
Christian Drabe, Dresden, DE;
Alexander Wolter, Dresden, DE;
Roger Steadman, Aachen, DE;
Andreas Bergmann, Steina, DE;
Gereon Vogtmeier, Aachen, DE;
Ralf Dorscheid, Aachen, DE;
Christian Drabe, Dresden, DE;
Alexander Wolter, Dresden, DE;
Roger Steadman, Aachen, DE;
Andreas Bergmann, Steina, DE;
Gereon Vogtmeier, Aachen, DE;
Ralf Dorscheid, Aachen, DE;
Fraunhofer-Gesellschaft zur Forderung der Angewandten Forschung E.V., Munich, DE;
Koninklijke Philips Electronics, N.V., Eindhoven, NL;
Abstract
The invention relates to semiconductor substrates and methods for producing such semiconductor substrates. In this connection, it is the object of the invention to provide semiconductor substrates which can be produced more cost-effectively and with which a high arrangement density as well as good electrical conductivity and closed surfaces can be achieved. In accordance with the invention, an electrically conductive connection is guided from its front side through the substrate up to the rear side. The electrically conductive connection is completely surrounded from the outside. The insulator is formed by an opening which is filled with material. The inner wall is provided with a dielectric coating and/or filled with an electrically insulating or conductive material. The electrically conductive connection is formed with a further opening which is filled with an electrically conductive material and is arranged in the interior of the insulator. The openings are formed with step-free inner walls aligned orthogonally to the front side or tapering continuously in the direction of the rear side.