The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 15, 2013
Filed:
Sep. 15, 2010
Sangyong Yoon, Seoul, KR;
Jinman Han, Seongnam-si, KR;
Kitae Park, Seongnam-si, KR;
Joon Young Kwak, Seongnam-si, KR;
Sangyong Yoon, Seoul, KR;
Jinman Han, Seongnam-si, KR;
Kitae Park, Seongnam-si, KR;
Joon Young Kwak, Seongnam-si, KR;
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
A nonvolatile memory includes a plurality of N-bit multi-level cell (MLC) memory cells and a controller. The plurality of N-bit MLC memory cells are for storing N pages of data, each of the MLC memory cells programmable into any one of 2threshold voltage distributions, where N is a positive number. The controller is configured to program the N pages of data into the MLC memory cells, and to execute a partial interleave process in which the N pages of data are divided into M page groups, where M is a positive number and where each page group includes at least one of the N pages of data, and in which each of the M page groups is applied to an error correction code (ECC) circuit to generate parity bits for the respective M page groups, where a bit-error rate (BER) among the pages within each of the M groups is equalized by the partial interleave process.