The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 15, 2013
Filed:
Jul. 22, 2009
Ji-hyun Kwon, Seoul, KR;
Hye-seok NA, Seoul, KR;
Won-hee Lee, Seoul, KR;
Ho-kyoon Kwon, Seoul, KR;
Byoung-sun NA, Hwaseong-si, KR;
Dong-yoon Lee, Seoul, KR;
Ju-hee Lee, Cheonan-si, KR;
Gwang-bum Ko, Asan-si, KR;
Ji-Hyun Kwon, Seoul, KR;
Hye-Seok Na, Seoul, KR;
Won-Hee Lee, Seoul, KR;
Ho-Kyoon Kwon, Seoul, KR;
Byoung-Sun Na, Hwaseong-si, KR;
Dong-Yoon Lee, Seoul, KR;
Ju-Hee Lee, Cheonan-si, KR;
Gwang-Bum Ko, Asan-si, KR;
Samsung Display Co., Ltd., , KR;
Abstract
A liquid crystal display (LCD), according to an exemplary embodiment of the present invention, includes a first pixel formed between the first and second gate lines, the first and the second data lines, a first subpixel configured to have applied thereto a first data voltage and a second subpixel configured to have applied thereto a second data voltage lower than the first data voltage, a second pixel formed between the second and third gate lines, the first and second data lines, and having a third subpixel configured to have applied thereto a third data voltage and a fourth subpixel configured to have applied thereto a fourth data voltage lower than the third data voltage. The first subpixel and the third subpixel are connected to a first thin film transistor and a third thin film transistor respectively, the first thin film transistor and the third thin film transistor have source electrodes connected to the first data line and the second data line respectively, and each of the source electrodes has an open portion surrounding a portion of a drain electrode, and wherein an open direction of the source electrode of the first thin film transistor is opposite to an open direction of the source electrode of the third thin film transistor.