The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 08, 2013
Filed:
Feb. 28, 2011
Larry J Thayer, Fort Collins, CO (US);
Larry J Thayer, Fort Collins, CO (US);
Avago Technologies Enterprise IP (Singapore) Pte. Ltd., Singapore, SG;
Abstract
Systems and methods for distribution analysis of a stacked-die integrated circuit (IC) are described. The stacked-die integrated circuit includes a primary die, and clock load information for the primary die of the IC is determined. Additionally, a clock load model may be created using the clock load information for the primary die. Clock load information for a second die that is coupled to the primary die may also be determined. The clock load information for the second die may be incorporated into the clock load model to create an enhanced clock load model of the stacked-die IC, which may then be analyzed as if a single-die IC.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile