The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 08, 2013
Filed:
Feb. 23, 2012
Jason R. Baumgartner, Austin, TX (US);
Paul Joseph Roessler, Austin, TX (US);
Ohad Shacham, Israel, IL;
Jiazhao Xu, Mount Kisco, NY (US);
Jason R. Baumgartner, Austin, TX (US);
Paul Joseph Roessler, Austin, TX (US);
Ohad Shacham, Israel, IL;
Jiazhao Xu, Mount Kisco, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A technique for verification of a logic design using a liveness-to-safety conversion includes assigning liveness gates for liveness properties of a netlist and assigning a single loop gate to provide a loop signal for the liveness gates. Assertion of the single loop gate is prevented when none of the liveness gates are asserted. A first state of the netlist is sampled and the sampled first state provides an initial state for a first behavioral loop for at least one of the liveness gates following the assertion of the single loop gate. The sampled first state of the first behavioral loop is compared with a later state of the first behavioral loop to determine if the sampled first state is repeated. A liveness violation is returned when the sampled first state is repeated and an associated one of the liveness gates remains asserted for a duration of the first behavioral loop.