The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 08, 2013

Filed:

Aug. 09, 2006
Applicants:

Kevin Charles Burke, Raleigh, NC (US);

Brian Michael Stempel, Raleigh, NC (US);

Daren Streett, Apex, NC (US);

Kevin Allen Sapp, Cary, NC (US);

Leslie Mark Debruyne, Cary, NC (US);

Nabil Amir Rizk, Apex, NC (US);

Thomas Andrew Sartorius, Raleigh, NC (US);

Rodney Wayne Smith, Raleigh, NC (US);

Inventors:

Kevin Charles Burke, Raleigh, NC (US);

Brian Michael Stempel, Raleigh, NC (US);

Daren Streett, Apex, NC (US);

Kevin Allen Sapp, Cary, NC (US);

Leslie Mark DeBruyne, Cary, NC (US);

Nabil Amir Rizk, Apex, NC (US);

Thomas Andrew Sartorius, Raleigh, NC (US);

Rodney Wayne Smith, Raleigh, NC (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

A processor is operative to execute two or more instruction sets, each in a different instruction set operating mode. As each instruction is executed, debug circuit comparison the current instruction set operating mode to a target instruction set operating mode sent by a programmer, and outputs an alert or indication in they match. The alert or indication may additionally be dependent upon the instruction address following within a predetermined target address range. The alert or indication may comprise a breakpoint signal that halts execution and/or it is output as an external signal of the processor. The instruction address at which the processor detects a match in the instruction set operating modes may additionally be output. Additionally or alternatively, the alert or indication may comprise starting or stopping a trace operation, causing an exception, or any other known debugger function.


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