Parallel read functional unit for microprocessors

Abstract

A functional unit for a microprocessor is provided, which allows for fast, parallel data read, write, and manipulation operations in the microprocessor that are useful for a number of software applications, such as cryptography. The functional unit includes first and second source registers for receiving first and second data items to be processed by the functional unit, first and second banks of memory tables, a combinational logic circuit, and a decoder. The first and second banks of memory tables are in communication with the first source register, and each of the tables is indexed by an index comprising a portion of the first data item received by the first source register. Each index points to a lookup result in a respective one of the memory tables. The combinational logic circuit is in communication with the first and second banks of memory tables and the second source register, receives the lookup results, and processes the lookup results and the second data item in the second source register to produce a result data item. The decoder circuit is in communication with the combinational logic circuit, and extracts an operational code from an instruction supplied to the functional unit, decodes the operational code, and controls the combinational logic circuit in accordance with the operational code.