The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8350597 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 08, 2013

Filed:

Oct. 07, 2009
Applicant:

Jean-robert Tourret, Cormelles le Royal, FR;

Inventor:

Jean-Robert Tourret, Cormelles le Royal, FR;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/153 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention relates to a low-voltage self-calibrated peak detector (). Using a two-step calibration process that compensates the offset errors introduced by the respective first, second and third comparators (), the peak detection is made accurate whatever temperature, process or mismatch spreads. Its input bandwidth can be as high as the bandwidth of an operational amplifier of unity gain. In a rail-to-rail configuration, it can be implemented into a fully differential low-voltage self-calibrated CMOS peak detector (), which can have a very high conversion gain (α) and a very high input signal dynamic ranging.


Find Patent Forward Citations

Tourret, Jean-Robert. (2013). Low voltage self calibrated cmos peak detector (U.S. Patent No. 8350597). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8350597

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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