The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8350596 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 08, 2013

Filed:

Mar. 26, 2010
Applicant:

Lip Kai Soh, Sitiawan, MY;

Inventor:

Lip Kai Soh, Sitiawan, MY;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 5/19 (2006.01);
U.S. Cl.
CPC ...
Abstract

A clock loss detection circuit is presented. The clock loss detection has two edge detection circuits and a clock loss detect counter circuit. Each edge detection circuit includes a reset signal circuit that generates a reset signal in response to a transition of a clock signal, and the reset signal circuit is connected to a clock input of the edge detection circuit. Each edge detection circuit also has a multiplexer connected to the reset signal circuit, and another multiplexer connected to the clock input. The clock loss detect counter circuit is connected to the edge detection circuits so that the clock loss detect counter circuit receives the reset signal from the second edge detection circuit and the clock signal from the first edge detection circuit.


Find Patent Forward Citations

Soh, Lip. (2013). Clock loss detection circuit for pll clock switchover (U.S. Patent No. 8350596). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8350596

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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