The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 08, 2013
Filed:
Jul. 10, 2008
Heimo Scheucher, Langegg, AT;
Guido Dormans, Bemmel, NL;
Tonny Kamphuis, Lent, NL;
NXP B.V., Eindhoven, NL;
Abstract
Integrated circuits () on a wafer comprise a wafer substrate (), a plurality of integrated circuits () formed lattice-like in rows and columns on the wafer substrate (), and first and second saw lines () separating the integrated circuits (). The first saw lines () run parallel and equidistant with respect to each other in a first direction (x) defined by the rows and the second saw lines () run parallel and equidistant with respect to each other in a second direction (y)defined by the columns. The integrated circuits () on the wafer further comprise a plurality of process control modules () formed on the wafer substrate () such that a given process control module () of the plurality of process modules () is bounded by two consecutive first saw lines () as well as by two consecutive second saw lines ().