The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 01, 2013
Filed:
Dec. 22, 2010
George A. Gonzalez, Austin, TX (US);
Pete J. Hannan, Austin, TX (US);
William A. Mcgee, San Jose, CA (US);
Vasant Palisetti, Santa Clara, CA (US);
Ashok Venkatachar, Santa Clara, CA (US);
George A. Gonzalez, Austin, TX (US);
Pete J. Hannan, Austin, TX (US);
William A. McGee, San Jose, CA (US);
Vasant Palisetti, Santa Clara, CA (US);
Ashok Venkatachar, Santa Clara, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method and apparatus for modifying a synchronous logic network so that the hold slack calculated at all pins is greater than or equal to a user-specified threshold, with the condition that the setup slack at any pin does not become negative or smaller than a user-specified margin. The result is an improved design which is less likely to fail due to a hold time violation. The method and apparatus introduce a limited number of logic cells which helps keep power consumption and design size to a minimum.