The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 01, 2013
Filed:
Jan. 09, 2009
Joerg Walter, Tuebingen, DE;
Lothar Felten, Hauset, BE;
Volker Urban, Boeblingen, DE;
Norbert Schumacher, Neuhausen, DE;
Marcel Naggatz, Coswig, DE;
Joerg Walter, Tuebingen, DE;
Lothar Felten, Hauset, BE;
Volker Urban, Boeblingen, DE;
Norbert Schumacher, Neuhausen, DE;
Marcel Naggatz, Coswig, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for simulating an operation of a digital circuit () is described. The method utilizes cycle simulation, wherein in a cycle based simulation model () of the digital circuit () components () of the digital circuit () are clocked synchronously every cycle () of a functional clock (Clk). According to the invention, real digital circuit (), i.e. chip or combinatorial logic (), timing information is included in the cycle simulation by inserting delay latches () into the cycle based simulation model () of the digital circuit (), wherein a non-functional clock (Sim clock) is used to clock the delay latches (), so that each delay latch () delays the propagation of a signal (I, J, K) by a cycle () of the non-functional clock (Sim clock).