The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 01, 2013
Filed:
Jun. 01, 2011
Yan Zhu, Macau, CN;
Chi-hang Chan, Macau, CN;
U-fat Chio, Macau, CN;
Sai-weng Sin, Macau, CN;
Seng-pan U, Macau, CN;
Rui Paulo Da Silva Martins, Macau, CN;
Franco Maloberti, Torre d'Isola, IT;
Yan Zhu, Macau, CN;
Chi-Hang Chan, Macau, CN;
U-Fat Chio, Macau, CN;
Sai-Weng Sin, Macau, CN;
Seng-Pan U, Macau, CN;
Rui Paulo Da Silva Martins, Macau, CN;
Franco Maloberti, Torre d'Isola, IT;
University of Macau, Macau, CN;
Abstract
The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DACarray and a sampling capacitor C, an n-type capacitor network including a DACarray and a sampling capacitor C; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch.