The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2013

Filed:

Feb. 15, 2011
Applicant:

Minoru Fukuda, Sayama, JP;

Inventor:

Minoru Fukuda, Sayama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A PLL circuit is provided capable of reducing phase noise and facilitating design. In the PLL circuit, a PLL receives a reference frequency and an output from a VC-TCXO, performs a lock operation. In a lock state, a selector selects an output of a first divider that divides the reference frequency. When PLL detects input of reference frequency being lost or an unlock state, the PLL outputs an alarm signal to the selector. When receiving the alarm signal from the PLL, the selector switches from the output of the first divider to an output of a second divider that frequency-divides an output of the VC-TCXO, and outputs the same. Then, a PLL receives an output of the selector and an output of a VCXO and performs a lock operation.


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