The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 01, 2013

Filed:

Nov. 25, 2008
Applicants:

Paul W. Sanders, Scottsdale, AZ (US);

Robert E. Jones, Austin, TX (US);

Michael F. Petras, Phoenix, AZ (US);

Chandrasekaram Ramiah, Phoenix, AZ (US);

Inventors:

Paul W. Sanders, Scottsdale, AZ (US);

Robert E. Jones, Austin, TX (US);

Michael F. Petras, Phoenix, AZ (US);

Chandrasekaram Ramiah, Phoenix, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01);
U.S. Cl.
CPC ...
Abstract

3-D ICs () with integrated passive devices (IPDs) () having reduced cross-talk and high packing density are provided by stacking separately prefabricated substrates () coupled by through-substrate-vias (TSVs) (). An active device (AD) substrate () has contacts on its upper portion (). An isolator substrate () is bonded to the AD substrate () so that TSVs () in the isolator substrate () are coupled to the contacts () on the AD substrate (), and desirably has an interconnect zone () on its upper surface. An IPD substrate () is bonded to the isolator substrate () so that TSVs () therein are coupled to the interconnect zone () on the isolator substrate () and/or TSVs () therein. The IPDs () are formed on its upper surface and coupled by TSVs () in the IPD () and isolator () substrates to devices () in the AD substrate (). The isolator substrate () provides superior IPD () to AD () cross-talk attenuation while permitting each substrate () to have small high aspect ratio TSVs (), facilitating high circuit packing density and efficient manufacturing.


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