The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8344427 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 01, 2013

Filed:

Jul. 31, 2012
Applicant:

Hiroshi Omura, Kanagawa, JP;

Inventor:

Hiroshi Omura, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/118 (2006.01);
U.S. Cl.
CPC ...
Abstract

The chip area of a semiconductor device having a plurality of standard cells is to be made smaller. A semiconductor device includes first and second standard cells. The first standard cell includes a diffusion region, a functional device region opposed to the diffusion region, and a metal layer. The second standard cell includes another diffusion region continuous with the diffusion region, another functional device region opposed to the other diffusion region, and further another diffusion region formed between the other diffusion region and the other functional device region. The metal layer and the other functional device region are coupled together electrically through the diffusion regions.


Find Patent Forward Citations

Omura, Hiroshi. (2013). Standard cell, semiconductor device having standard cells, and method for laying out and wiring the standard cell (U.S. Patent No. 8344427). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8344427

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