The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 01, 2013
Filed:
Nov. 17, 2008
Vladimir Anatolyevich Aksyuk, Westfield, NJ (US);
Nagesh R Basavanhally, Skillman, NJ (US);
Avinoam Kornblit, Highland Park, NJ (US);
Warren Yiu-cho Lai, Chatham Township, NJ (US);
Joseph Ashley Taylor, Springfield, NJ (US);
Robert Francis Fullowan, Berkeley Heights, NJ (US);
Vladimir Anatolyevich Aksyuk, Westfield, NJ (US);
Nagesh R Basavanhally, Skillman, NJ (US);
Avinoam Kornblit, Highland Park, NJ (US);
Warren Yiu-Cho Lai, Chatham Township, NJ (US);
Joseph Ashley Taylor, Springfield, NJ (US);
Robert Francis Fullowan, Berkeley Heights, NJ (US);
Alcatel Lucent, Paris, FR;
Abstract
Apparatus including a chip substrate having a first chip surface facing away from a second chip surface; an array of microelectronic elements on the first chip surface; and an array of conductors each in communication with one of the microelectronic elements, the conductors passing through the chip substrate and fully spanning a distance between the first and second chip surfaces. Process including: providing an apparatus including a chip substrate having a first chip surface facing away from a second chip surface, an array of microelectronic elements being on the first chip surface, an array of conductors each being in communication with one of the microelectronic elements and partially spanning an average distance between the first and second chip surfaces; bonding a temporary support carrier onto the array of microelectronic elements; removing a portion of the chip substrate, thereby reducing the average distance between the first and second chip surfaces; and forming an under bump metallization pad at the second chip surface in electrical communication with a conductor.