Method, apparatus, and system for analyzing operation of semiconductor integrated circuits

Abstract

An operation analyzing apparatus () for semiconductor integrated circuits according to this exemplary embodiment includes a simulation analyzing unit (), and the simulation analyzing unit () includes: a semiconductor characteristics extracting unit () that extracts the inductances L, resistances R, and capacitances C of a board, a package, and a semiconductor integrated circuit, from the semiconductor integrated circuit mounted on the board via the package; an individual network generating unit () that generates individual networks of the extracted inductance L, resistance R, and capacitance C with respect to each of said semiconductor substrate, said package, and said semiconductor integrated circuit; an integrated network generating unit () that generates an integrated network by integrating all of the generated individual networks; and an operation simulation running unit () that performs an operation simulation of the semiconductor integrated circuit by inserting a test noise pattern to an arbitrary position in the generated integrated network.